Clock Stretching:
Clock stretching is a phenomenon where the I2C slave pulls the SCL line low on the 9th clock of every I2C data transfer. The clock is pulled low when the CPU is processing the I2C interrupt to evaluate either the address or process a data received from Master or to prepare the next data when Master is reading from the slave.
Why needed?
When the master is reading from the slave, its the slave that places the data on the SDA line, but its the master that controls the clock. If the slave is not ready to send the data, the microprocessor on the slave device will need to go to an interrupt routine, save its working registers, find out what address the master wants to read from, get the data and place it in its transmission register. The master is blissfully sending out clock pulses on the SCL line that the slave cannot respond to. That time clock stretching is needed. In this time, the slave is allowed to hold the SCL line low. The I2C slave holds down the SCL line and the master should wait until it goes high which indicates that the slave is ready to send data.
Clock stretching is a phenomenon where the I2C slave pulls the SCL line low on the 9th clock of every I2C data transfer. The clock is pulled low when the CPU is processing the I2C interrupt to evaluate either the address or process a data received from Master or to prepare the next data when Master is reading from the slave.
Why needed?
When the master is reading from the slave, its the slave that places the data on the SDA line, but its the master that controls the clock. If the slave is not ready to send the data, the microprocessor on the slave device will need to go to an interrupt routine, save its working registers, find out what address the master wants to read from, get the data and place it in its transmission register. The master is blissfully sending out clock pulses on the SCL line that the slave cannot respond to. That time clock stretching is needed. In this time, the slave is allowed to hold the SCL line low. The I2C slave holds down the SCL line and the master should wait until it goes high which indicates that the slave is ready to send data.
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